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harvard university developed nanocomputer!哈佛大学开发出纳米处理器纳米电脑programable nanoprocessor

 Nanowire tiles can perform arithmetic and logical
functions and are fully scalable

 CONTACT: Caroline Perry , 617-496-3815
Cambridge, Mass. – February 9, 2011 – Engineers
and scientists collaborating at Harvard University and
the MITRE Corporation have developed and
demonstrated the world’s first programmable
The groundbreaking prototype computer system,
described in a paper appearing today in the journal
Nature , represents a significant step forward in the
complexity of computer circuits that can be assembled
from synthesized nanometer-scale components.
It also represents an advance because these ultra-tiny
nanocircuits can be programmed electronically to
perform a number of basic arithmetic and logical
"This work represents a quantum jump forward in the
complexity and function of circuits built from the
bottom up, and thus demonstrates that this bottom-up
paradigm, which is distinct from the way commercial
circuits are built today, can yield nanoprocessors and
other integrated systems of the future,” says principal
investigator Charles M. Lieber, who holds a joint
appointment at Harvard's Department of Chemistry and
Chemical Biology and School of Engineering and
Applied Sciences.
The versatile, nanoscale circuits are assembled into
tiny tile-like nanoprocessors from sets of precisely
engineered and fabricated germanium-silicon wires
with functional oxide shells, having a total diameter of
only 30 nanometers. Shown here are atomic force (left)
and optical microscopy (center) images of a
programmable nanowire nanoprocessor, and a
corresponding schematic (right) of the nanowire circuit
architecture. Image courtesy of Charles M. Lieber.
The work was enabled by advances in the design and
synthesis of nanowire building blocks. These nanowire
components now demonstrate the reproducibility
needed to build functional electronic circuits, and also
do so at a size and material complexity difficult to
achieve by traditional top-down approaches.
Moreover, the tiled architecture is fully scalable,
allowing the assembly of much larger and ever more
functional nanoprocessors.
“For the past 10 to 15 years, researchers working with
nanowires, carbon nanotubes, and other nanostructures
have struggled to build all but the most basic circuits,
in large part due to variations in properties of
individual nanostructures,” says Lieber, the Mark
Hyman Professor of Chemistry. “We have shown that
this limitation can now be overcome and are excited
about prospects of exploiting the bottom-up paradigm
of biology in building future electronics.”
An additional feature of the advance is that the circuits
in the nanoprocessor operate using very little power,
even allowing for their miniscule size, because their
component nanowires contain transistor switches that
are “nonvolatile.”
This means that unlike transistors in conventional
microcomputer circuits, once the nanowire transistors
are programmed, they do not require any additional
expenditure of electrical power for maintaining
“Because of their very small size and very low power
requirements, these new nanoprocessor circuits are
building blocks that can control and enable an entirely
new class of much smaller, lighter weight electronic
sensors and consumer electronics,” says co-author
Shamik Das, the lead engineer in MITRE’s
Nanosystems Group.
“This new nanoprocessor represents a major milestone
toward realizing the vision of a nanocomputer that was
first articulated more than 50 years ago by physicist
Richard Feynman,” says James Ellenbogen, a chief
scientist at MITRE.
Co-authors on the paper included four members of
Lieber’s lab at Harvard: Hao Yan (Ph.D. '10), SungWoo
Nam (Ph.D. '10), Yongjie Hu (Ph.D. '10), and doctoral
candidate Hwan Sung Choe, as well as collaborators at
The research team at MITRE comprised Das,
Ellenbogen, and nanotechnology laboratory director Jim
Klemic. The MITRE Corporation is a not-for-profit
company that provides systems engineering, research
and development, and information technology support
to the government. MITRE’s principal locations are in
Bedford, Mass., and McLean, Va.
The research was supported by a Department of
Defense National Security Science and Engineering
Faculty Fellowship, the NanoEnabled Technology
Initiative, and the MITRE Innovation Program.
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False-colour scanning electron microscopy image of a
programmable nanowire nanoprocessor super-
imposed on a schematic nanoprocessor circuit
architecture. Photo courtesy of Charles M. Lieber.nanoprocessor constructed from intrinsically nanometre-scale building blocks is an essential component for controlling memory, nanosensors and other functions proposed for nanosystems assembled from the bottom up1, 2, 3. Important steps towards this goal over the past fifteen years include the realization of simple logic gates with individually assembled semiconductor nanowires and carbon nanotubes1, 4, 5, 6, 7, 8, but with only 16 devices or fewer and a single function for each circuit. Recently, logic circuits also have been demonstrated that use two or three elements of a one-dimensional memristor array9, although such passive devices without gain are difficult to cascade. These circuits fall short of the requirements for a scalable, multifunctional nanoprocessor10, 11 owing to challenges in materials, assembly and architecture on the nanoscale. Here we describe the design, fabrication and use of programmable and scalable logic tiles for nanoprocessors that surmount these hurdles. The tiles were built from programmable, non-volatile nanowire transistor arrays. Ge/Si core/shell nanowires12 coupled to designed dielectric shells yielded single-nanowire, non-volatile field-effect transistors (FETs) with uniform, programmable threshold voltages and the capability to drive cascaded elements. We developed an architecture to integrate the programmable nanowire FETs and define a logic tile consisting of two interconnected arrays with 496 functional configurable FET nodes in an area of ~960?μm2. The logic tile was programmed and operated first as a full adder with a maximal voltage gain of ten and input–output voltage matching. Then we showed that the same logic tile can be reprogrammed and used to demonstrate full-subtractor, multiplexer, demultiplexer and clocked D-latch functions. These results represent a significant advance in the complexity and functionality of nanoelectronic circuits built from the bottom up with a tiled architecture that could be cascaded to realize fully integrated nanoprocessors with computing, memory and addressing capabilities.

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